The present invention relates generally to electronics circuits, and more specifically to techniques for generating clock signals with continuous phase.
Clock signals are commonly used in various electronics circuits such as personal computers, consumer electronics, network equipments, and so on. Clock signals are widely used for digital circuits, e.g., to trigger synchronous circuits such as flip-flops. Clock signals are also used for analog circuits, e.g., to generate local oscillator (LO) signals used for frequency upconversion and downconversion. A clock signal is often generated using a phase-locked loop (PLL).
FIG. 1 shows a conventional clock generator 100, which consists of a PLL 110 and a divider 120. PLL 110 includes a phase detector 112, a loop filter 114, a voltage controlled oscillator (VCO) 116, and a divider 118. VCO 116 generates a VCO signal having a frequency determined by a control signal from loop filter 114. Divider 118 divides the VCO signal by a factor of M in frequency and provides a feedback signal. Phase detector 112 receives a reference signal and the feedback signal from divider 118, compares the phases of the two signals, and provides a detector signal that is proportional to the detected phase difference between the two signals. Loop filter 114 filters the detector signal and provides the control signal for VCO 116. Loop filter 114 adjusts the control signal such that the frequency of the feedback signal is locked to that of the reference signal. Divider 120 divides the VCO signal by a factor of N in frequency and provides an output clock signal. M and N are integers that may be one or greater.
In clock generator 100, divider 118 is effectively used to multiply the reference signal by a factor of M in frequency to produce the VCO signal. Since divider 118 is in the feedback path of PLL 110, phase detector 112 provides the appropriate adjustments to loop filter 114 to maintain frequency lock between the feedback signal and the reference signal. When locked, the VCO signal has a frequency that is M times that of the reference signal. Divider 120 simply divides down the VCO signal by a factor of N in frequency. The output clock frequency, fout, may be expressed in terms of the reference signal frequency, fref, as follows:
                              f          out                =                              M            N                    ·                                    f              ref                        .                                              Eq        ⁢                                  ⁢                  (          1          )                    
Conventional clock generator 100 has several key limitations. A first key limitation is the inability to achieve a precise output clock frequency. Equation (1) indicates that the desired output clock frequency, fout, can be obtained by selecting suitable values for M and N for a given reference frequency, fref. However, the possible values for M are constrained to be within a specified range, which is determined by the frequency range of VCO 116 as well as the reference frequency. For example, if the VCO has an operating frequency range of 320 MHz to 640 MHz and the reference frequency is 20 MHz, then M is constrained to be between 16 and 32. In this example, it would not be possible to generate an output clock with a frequency of 17.25 MHz. Improved precision may be achieved by adjusting the reference frequency. However, this is undesirable or not practical in many instances. A second key limitation of clock generator 100 is the inability to generate multiple output clock signals having flexible frequencies. Multiple dividers 120 may be used to divide down the VCO signal with different N integer values to obtain clock signals at different frequencies. However, the frequencies of these clock signals would be restricted to integer divisors of the VCO signal frequency, fvco, or fout 1=fvco/N1, fout 2=fvco/N2, and so on.
A clock device with multiple PLLs can generate multiple clock signals having different and more flexible frequencies. Each PLL may be operated with a different set of M and N values to allow for greater precision in the output clock frequency. However, the multiple-PLL design also has several disadvantages. First, using multiple PLLs on a single monolithic device is often problematic because of noise coupling between the PLLs (i.e., the noise from one PLL interacting with another PLL), which can degrade performance. Second, the same reference signal is typically used for all PLLs within the device, which then limits the precision that can be achieved for the output clock frequencies. For the example described above, output clocks of 17.5 MHz and 34.5 MHz cannot be obtained for a reference frequency of 20 MHz even if multiple PLLs are employed. Third, a larger die size is required to fabricate the multiple PLLs, which increases cost. A PLL typically employs capacitors for charge reservoirs that maintain the control voltages for the loop filter and the VCO and for power supply noise filtering. For some PLL designs, these capacitors may occupy a large percentage (e.g., 80 to 90 percent) of the total die area for the PLL. The use of multiple PLLs thus incurs a substantial penalty in die area.
As can be seen, techniques that can generate clock signals with good frequency resolution and which avoid the disadvantages described above for the multiple-PLL design are highly desirable.